How to build and test a module
1.test have: generate 、stimulus 、check 、respose
2.only one monitor can be active at any time
3.$finish VS $finish(2)
$finish(2) print about cpu / memory information
4.parameter defparam
defparam ===> redefine parameters (cross module)
modulename #(parameter1(parameter_value),….)(port_declaratoin); <==常见
5.tasks and functions are declared wihin modules
1. tasks may only be used in procedural blocks.
A task invocation or task enable as it is called in verilog , is a statememt by itself .
It may not be used as operands in an expression.
2.functions are used as operands in expressions
A function may be used in either a procedural block or
a continuous assignment,or indeed,any place where an expression may appear
6.if task statmemts inside can synthesys ====> task can synthesys
if task statmemts inside can not synthesys ====> task can not synthesys
task may have time or delay control
7.function not have time or delay control
if function statmemts inside can synthesys ====> function can synthesys
if function statmemts inside can not synthesy ====> function can not synthesys
8.system task
$display / $write /$strobe /$monitor
$write not add a newline character to the output string
$readmemb/$readmemh === store file into memory
$stop
$finish / $finish(2)
9.system function
$time <===返回64位数
$stime <===返回32位数
$random
…
conversion function:
$rtoi / $itor / $realtobits / $bitstoreal
10.XMR
verilog has a mechanism for globally referencing nets, registers,events,
tasks,and functions called the cross-module reference , or XMR.
11.Hierarchical Module
module A;
reg x; //1 <==A.x
…
task B;
reg x;//2 <==A.B.x
begin
…
begin : C
reg x; //3 <===A.B.C.x
..
end
end
endtask
initial
begin:D
reg x;//4 <===A.D.x
…
end
endmodule
12.verilog-2001 new features
(1).ANSI-style port lists
95style:一个signal 需要端口、方向、数据类型可能需要重复三次。
2K1style:把一个signal的端口、方向、数据类型全部放在一起申明。
(2).parameter
module module_name #(parameter_declaration)
(port_declaration);
(3)constant function
V2K1: log2
(4)comma separated sensitivity list
(5) combinational logic sensitivity list
推荐：
or b or sel)
不推荐：
always@(*)
(6)vector part select <==位宽选择
reg [63:0] vector1;
reg [0:63] vector2;
byte = vector1[31-:8];//vector1[31:24]
byte = vector1[24+:8];//vector1[31:24]
byte =vector2[31-:8];//vector2[24:31]
byte =vector2[24+:8];//vector2[24:31]
13.Multi-Demensional Array
in verilog-1995
only 1D arrays of reg / integer and time allowed
in verilog-2001
wire [31:0] array_1D[127:0];
real array_2D[127:0][127:0];
14.Array Bit and part selectin verilog-1995
reg [31:0] ram [0:255];
reg [7:0] high_byte;
reg [31:0] temp;
temp = ram[5];
high_byte=temp[31:24];
in verilog-2001
reg[31:0] ram[0:255];
reg[7:0] high_byte;
high_byte = ram[5][31:24];
15.power operator **
取2的10次方：1K=2**10
16.size and typed parameter <==95中,the width of a parameter must be 32bits
17.explicit in_line parameter pass
.parameter(parameter_value)
18.fixed local parameter
module multiplier(a,b,product);
parameter a_width = 8,b_width=8;
loaclparam product_width= a_width+b_width;
parameter :can be redifined by defparam or in_line parameter redefinition
localparam: cannot be refined(外面不可见)
19.generate <== use loops to generate any number of instances
generate
genvar i;
for(i=xx;i<=xx;i=i+1)
begin :indentifier
….
end
endgenerate